HDL Design |
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| Logic Implementation | Design and code logic blocks to design specification. Either from an existing specification or a specification written to reflect your requirements. Designs done with logic Synthesis as the goal. |
| Logic Validation | Simulation of design using Avsys provided Model Tech simulation tool or your selected flavor of simulation tool. VSS and Quick VHDL |
| Bus Functional Models | Build Bus Function Models from concept to implementation and validation. Use Bus Function Models. Debug and fix Bus Functional Models. |
| Test Bench |
Build test bench to validate design. Use existing BFM or code stimulus to drive design. Specify and generate tests to validate design. |
| Synthesis |
Done using Client provided tool. Scripts done using UNIX shell. Scripts done using Perl |
| Tool Expertise |
ModelSim licensed tool available for both VHDL and Verilog Simulation. Expert in use of VSS and Quick VHDL. Active HDL from Aldec used for statemachine and block diagrams. |